1. Field of the Invention
This invention is directed to a magnetic bubble domain circuit component, in general, and to a compact exchange switch which exchanges magnetic bubble domains between adjacent propagation paths in a magnetic bubble domain circuit, in particular.
2. Prior Art
Existing magnetic bubble domain circuits and systems utilize many kinds of components or devices. These components and devices are appropriately arranged to define paths for bubble domain propagation. In order to provide optimum utilization of magnetic bubble domain technology, it is frequently desirable to utilize systems or chip organizations having a plurality of such propagation paths. Typically, these paths may take the form of adjacent parallel paths, or adjacent loops and paths such as in a major/minor loop organization. The particular organization depends upon storage capacity desired, logic operations or the like. Some exchange switches require a large amount of operating time and space to exchange information from adjacent paths. Exchange switches of this type sometimes require as many as four (4) bits separation between two adjacent circuits in order to effect an appropriate exchange. These exchange switches typically take the form of a double switch arrangement. This requirement (i.e. a double switch arrangement) somewhat limited the minimum size of the data block which could be processed in the chip configuration. In addition, in the known prior art arrangements, the data blocks had to be closely synchronized by external control means in order to provide a workable system. These control means could include multiplexing techniques for better data throughout.
In known major/minor loop organizations, suitable transfer switches (e.g. the dollar ($) switch) are available. However, these transfer switches typically require all of the information in a loop to be removed (or stored) at one time. This is, transfer of information is permitted in only one direction at a time. The known transfer switches do not permit the concurrent exchange of information between the major and the minor loops. While the major/minor loop arrangement is faster than single storage loop arrangements, it is still relatively time consuming. Moreover, these arrangements are not very flexible in that entire blocks of information must be handled. Small portions of information blocks are not readily utilized. Thus, it is clear that the existing chip organizations and system arrangements require excessive amounts of chip capacity in order to effect exchange of information. In addition, the system is hampered in throughput rate because of extensive time requirements for data interchange.